The present invention relates to a method of fabricating a flash memory device and, more particularly, to a method of fabricating a flash memory device, in which, in a state where a back bias voltage is applied, an oxide layer of a dielectric layer is formed using a plasma oxidization process.
In general, non-volatile memory devices retain data stored therein when power is off. A unit cell of this non-volatile memory device includes a tunnel insulating layer, a floating gate, a dielectric layer, and a control gate all of which are sequentially stacked over an active area of a semiconductor substrate. The unit cell can store data as voltage from the outside to a control gate electrode is coupled to the floating gate. Thus, if it sought to store data at a low program voltage within a short period of time, the ratio of voltage applied to the control gate electrode and voltage induced to the floating gate has to be great.
The ratio of voltage applied to the control gate electrode and voltage induced to the floating gate is called a coupling ratio. The coupling ratio can be expressed by the ratio of the sum of capacitance of a tunnel insulating layer and a gate interlayer insulating layer and the sum of capacitance of the gate interlayer insulating layer.
In recent years, with the high integration of devices and the decreasing cell size, the capacitance of a dielectric layer, having a stacked layer of oxide-nitride-oxide (ONO), decreases and the coupling ratio is reduced. Due to this, in order to ensure the coupling ratio, the thickness of the dielectric layer has been decreased. However, if the thickness of the dielectric layer reduces, the leakage current increases and a charge retention characteristic is reduced, degrading the characteristics of devices.
In particular, the ONO dielectric layer is deposited using a dichlorosilane (DCS) or monosilane (MS)-based chemical vapor deposition (CVD) method. The oxide layer or the nitride layer formed by this CVD method has a film quality lower than that of an oxide layer formed by a typical dry or wet oxidization process and has a low step coverage characteristic of 85% or less. Recently, as the thickness of the dielectric layer decreases so as to ensure the coupling ratio because of the high-integrated devices, the leakage current and reliability characteristic are degraded. Consequently, there is a need for a method with excellent step coverage.